Adaptive Analog VLSI Signal Processing and Neural Networks

PREFACE While the digital world frantically pursues ever-faster clock speeds to satisfy demanding signal processing applications, a quiet revolution in analog computing has been brewing, which promises to do more with less — more sophisticated signal processing delivered at less power in a smaller space. Novel application of a digital memory technology, the floating-gate MOS-FET (used in EEPROMs), as an analog memory and computation device provides the basic building block of this technology. Utilization of inherent device physics provides the adap-tivity and programmability needed to realize compact reconfigurable analog VLSI systems. Floating-gate charge storage provides non-volatile memory for a matrix of coefficients, while the nonlinear current-voltage relation of the MOSFET provides signal-coefficient multiplication. Summation of products is achieved simply using Kirckhoffs Current Law. Matrix coefficients adapt according to a correlation learning rule which utilizes physical device phenomena (electron tunneling and hot-electron injection) to program floating-gate charge. All of this functionality costs only four transistors per coefficient, each operating at nanowatts of power consumption. The resultant adaptive analog matrix-vector operations form the core of a novel analog VLSI signal-processing model, which is called computing in memory. Peripheral circuitry determines learning behavior, controls programmability, and expands core matrix functionality. iv ACKNOWLEDGEMENTS I wish to thank my colleagues in the Integrated Computational Electronics lab for their encouragement and support, particularly Venkatesh Srinivasan for assistance with the design and construction of the adaptive test board, as well as producing some of the simulation results in Chapter 6. Figure 1 Classic picture of a two-layer neural network from the perspective of im-plementating these networks in hardware. The neural networks are layers of simple processors, called neurons, interconnected through weighting elements, called synapses. The neurons aggregate the incoming inputs (including a threshold or offset) and are applied through a tanh(·) non-linearity. The synapse elements, which in general are far more numerous than neuron elements, must multiply the incoming signal by an internally stored value, called the weight, and must adapt this weight based upon a particular learning rule. Learning rules implemented in silicon are typically functions of correlations of signals passing through each synapse processor. 2 Figure 2 Typical architectures for neural network implementations. Although the routing looks complicated in Fig.